Design of Diversified Low Power and High-Speed Comparators using 45nm Cmos Technology

At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback used design novel circuits. If the comparator having without clock signal. comparators mainly minimize good accuracy because of signal, if signal is there, it drive current. But in existed high These drawbacks overcome by using projected comparator. Projected reduced consumption, propagation delay, currents a smaller number transistors. useful analog digital converters. And this simulated 45 nm CMOS technology Cadence Virtuoso tool.